1. Field of the Invention
Embodiments of the invention generally relate to electronics, and in particular, to receivers for communication links using binary non-return-to zero (NRZ) as the method of transmission and in which multiples samples per baud period are available.
2. Description of the Related Art
In any communication channel, the ability of the receiver to accurately detect the transmitted data is impacted by the presence of channel impairments. Channel impairments can include both correlated and uncorrelated sources. A common example of correlated impairment is Inter-Symbol Interference (ISI), also sometimes referred to as Data Dependent Jitter (DDJ) in some fields of communication receivers.
As the amount of ISI increases, it becomes increasingly difficult for a receiver to correctly detect the transmitted information. If the amount of ISI increases enough, techniques to mitigate at least a portion of the ISI are typically used so that the receiver can function properly.
A very common technique to mitigate ISI is to apply an equalizer to the received signal. This can be done in the analog domain or in the digital domain after suitable conversion with an analog-to-digital converter (ADC). The equalizer is typically designed to have a frequency response that is approximately equal to or the reciprocal of the channel response inducing the ISI. For example, a low pass frequency response is common in communication channels. Mitigation of the ISI induced by the low-pass response can be achieved by applying an equalizer with a corresponding reciprocal high-pass frequency response or a pre-emphasis response or by negating the impairment via subtraction with an approximately equal low-pass frequency response.
The ability to mitigate channel dependent impairments allows a receiver to tolerate an increased amount of other impairments that are not as easily mitigated.
Modern receivers in use in many different fields of communication (such as wireless, serdes, reed channels, etc.), perform an increasing amount of channel impairment mitigation in the digital domain. The received signal is sampled multiple times per baud period with an ADC having a prescribed number of sample threshold levels. Increasing the number of samples per baud taken of the signal, and/or increasing the number of threshold levels used per sample, provides increasing fidelity in the digital domain of the received analog signal. This increased fidelity allows for better and stronger ISI mitigation techniques. Those versed in the art will recognize the application of Feed-Forward Equalizers (FFE) and Decision-Feedback Equalizers (DFE), as well as more complex Maximum Likelihood Sequence Estimators (MLSE), and other techniques, for these situations.
The product of the number of samples per baud period and the number of threshold levels per sample directly affects the cost and complexity of a receiving device. Much effort by designers is devoted to reducing the number of samples per baud used and/or reducing the number of thresholds per sample. Both approaches reduce the complexity of the receiver, but make it increasingly difficult to mitigate ISI. This is particularly true when reducing the number of amplitude thresholds per sample.
To reduce complexity of a receiver, it is desirable to sample a received signal with an ADC or slicer having only a single amplitude threshold. Multiple samples per baud period are available, but each sample has one of two possible values, depending on whether the received signal is greater in amplitude or lesser in amplitude than a set threshold.
To increase the usefulness of a receiver it is desirable for the receiver to mitigate and/or tolerate an increasing amount of correlated channel impairment (e.g., ISI or DDJ). With only 1 threshold level per sample, conventional equalizer-based techniques for mitigating correlated channel impairments will not work.
Embodiments of the invention advantageously increase the amount of correlated channel impairment that can be tolerated/mitigated by a receiver having only a single amplitude threshold per sample.
Current state of the art in decision feedback equalizer processing to combat correlated channel impairments is represented by the following U.S. Pat. Nos. 5,132,988; 7,606,301; 7,184,477; 6,192,072; and 6,363,112, which are incorporated by reference in their entirety and discussed in the following:
The concept of using current and past decisions to adjust the detection and determination of subsequent symbols is well established in the current art. A decision feedback equalizer (DFE) is a well recognized form of this concept. The common theme of systems employing this technique is that the amplitude of the received signal is preserved and processed, either in analog or digital domain. Variations exist on basic concept of the DFE.
U.S. Pat. No. 5,132,988 to Fisher, et al., the linear feedback structure of the DFE is replaced with a RAM table that is addressed by the current and recent history of the determined bits.
Another DFE implementation is described in U.S. Pat. No. 7,606,301 to Aziz, in which it is recognized that the optimal sampling phase for DFE operation may be different than that provided by a non-DFE based clock and data recovery (CDR) circuit.
A DFE described in U.S. Pat. No. 7,184,477 to Haunstein, et al., adjusts the decision threshold and the sample timing for the next baud interval based on at least the previous bit decision.
In U.S. Pat. No. 6,192,072, and U.S. Pat. No. 6,363,112, both to Azadet, et al., a parallel implementation of a DFE is disclosed. Implementation in a parallel architecture allows for much higher data rates than is possible with a linear implementation.
FIG. 1 illustrates a conventional SerDes system with a transmitter (data source 102) and a receiver (data receiver 106). Those knowledgeable in the art will recognize that there are numerous variations on this basic implementation architecture. For simplicity, the description is given with the assumption of a serial implementation. The circuit of FIG. 1 illustrates a generic timing recovery mechanism that aligns the data recovery window with the sampled data stream based on recent sample data. This function is typically present in the receiver 106. The timing recovery function can be performed with a feedback loop entirely within the digital domain or by controlling the frequency of the ADC sampling clock. A feed-forward timing recovery mechanism can also be employed, although this is not shown in FIG. 1.